1. Field of Invention
The invention is generally related to superconducting circuits and in particular to Josephson junctions made by the Selective Non-Anodizing Process (SNAP) as taught within U.S. patent application Ser. No. (179,311), now U.S. Pat. No. 4,421,785, for Josephson Tunnel Junction Device and Method of Manufacture to Harry S. Kroger. The present invention is particularly related to improved dimensional control of anodization within the SNAP by use of an anodizable mask, particularly one of aluminum. The present invention is also particularly related to a reduction in the number of steps, and simplification of steps, within the SNAP by utilization of the lift-off technique.
2. Description of the Prior Art
Superconductive circuits both for digital and analog applications which utilize Josephson tunneling are known in the art. It is important for high speed operation of digital circuits and for low noise properties of analog circuits constructed with Josephson junctions to have low capacitance in parallel to the junction.
The capacitance across the Josephson junction is composed of two parts: the capacitance between the two electrodes of the junctions and the stray capacitance of the connecting lines. The main way of reducing the junction capacitance when one is using any particular technology is to reduce the junction size.
The way to reduce the stray capacitance of the connecting lines is by adding a low dielectric insulator between the base layer and the interconnecting lines. Use of silicon monoxide (SiO) as such a dielectric insulator is reported by J. H. Grenier et al. in IBM J. Res Develop., Vol. 24 No. 2, March, 1980 [hereinafter Grenier] and use of silicon dioxide (SiO.sub.2) is reported by D. J. Jillie, L. N. Smith and H. Kroger in IEEE Transactions on Magnetics, Vol. MAG-19 No. 3, May, 1983, at Page 1170 [hereinafter Jillie]. Patterning of SiO is usually done by lift-off process while Jillie teaches that patterning of SiO.sub.2 is done by etching.
There are two major techniques for producing Josephson junctions. One method is by using a base layer of superconducting material taught by Grenier which has on top of it a pattern layer of insulator deposited in such a way that vias are left at the desired junction locations. Junctions are created at those locations either by oxidizing in order to create a native oxide, or by deposition of artificial barrier. A superconducting contact layer then has to be deposited and patterned on top of the junction. The main advantage of this method is freedom in the choice of the insulator. The disadvantage of this approach is the requirement for extra processing steps done at the interface layer of the junction which tend, including by risk of physical damage, to degrade its properties.
The second major method making junctions is by the SNAP (Selective Non-Anodizing Process), the common name given to the process taught in U.S. patent application Ser. No. (179,311), now U.S. Pat. No. 4,421,785, for Josephson Tunnel Junction Device and Method of Manufacture to Harry S. Kroger [hereinafter Kroger]. In the SNAP process a tri-layer of superconductor, barrier and superconductor are deposited uninterrupted. As in the first method, the barrier can be either native oxide or an artificial barrier. However, in accordance with the SNAP method, the junctions are defined by anodizing all the non-junction areas. The advantage of this SNAP method is the maintenance of clean conditions during the deposition of the junction. The disadvantage of this SNAP method is the limitation in the choice of insulator both in available thickness and the dielectric constant of the insulator. The insulator is only the oxide produced by anodization, normally niobium-penta oxide (Nb.sub.2 O.sub.5), which exhibits properties of thickness and dielectric constant which contribute to a larger than desired stray capacitance. Another disadvantage of the SNAP method relevant to the present invention is resultant from difficulties with the anodizing process. During the anodization free negative oxygen ions from the liquid solution are being driven into the metal by the positive potential thereof. As a result oxide is created. The volume of the oxide is bigger than the original metal and therefore the material swells. By applying higher anodization voltage more and more oxygen penetrates the top-most oxide. The swelling of the anodized material next to the photo resist mask which defines the junctions tends to lift the mask and anodize underneath it. As a result the achievable resolution is limited by the mechanical properties of the photo resist. Furthermore, in order to achieve better ion mobility of the oxygen in the anodized layer during the anodization, it is desirable to use a hot anodizing solution. Conventional photo resists cannot withstand this hot solution. A way to overcome these photo resist limitations is by the use of deposited insulator mask. Such a process using silicon dioxide is taught by L. N. Smith, H. Kroger, and D. W. Jillie in IEEE Transaction on Magnetics Vol. MAG-19 No. 3, May, 1983 at page 787 [hereinafter Smith]. This paper is an update to the teaching of U.S. patent application Ser. No. (252,528), now U.S. Pat. No. 4,430,662, for Superconductng Tunnel Junction Integrated Circuit and Method of Manufacture Thereof to D. W. Jillie and L. N. Smith [hereinafter Jillie], which patent was filed on equal date with and which contains complementary teaching to the aforementioned Kroger patent.
The improvement to the SNAP method taught by Jillie which calls for the use of a deposited insulator mask is still subject to disadvantages, however. The deposition of the insulator tends to physically damage the top layer of superconductor over the junction due to the fact that this layer of superconductor has to be thin in order to facilitate the anodization. Any damage to this thin superconductor will degrade the junction properties. The capacitance resultant from the high dielectric constant of the anodized material can be reduced by depositing extra insulator. This insulator can be chosen according to its dielectric and mechanical properties but this insulator requires extra photolithographic processing with critical alignment over the junctions.
A common method for patterning deposted thin film is the well known lift-off method, the techniques for which are discussed in the article Lift-Off Tecniques for Fine Line Metal Patterning by J. M. Frary and P. Seese appearing in Semiconductor International for December 1981 at page 72. With the lift-off method a stencil, usually made out of photo resist, is patterned and then the required material (the insulator of Jillie) is deposited on top of it. By removing the stencil one is left with the required pattern. The lift-off method can achieve high resolution and is useful with hard to etch materials such as silicon oxide (SiO) or when one cannot find a selective etching method for different layers. In order to achieve easy removal of the stencil, it is necessary that its thickness will be higher than the deposited material. It is also desirable to have extended lips around the edge of the stencil in such a way that it will create a discontinuity in the deposited material, this discontinuity enabling the removal of the stencil and the excess material deposited on top of it.